Hardware that interfaces to a switch needs to buffer ingress cells before sending them to the switch. This buffering is required because the switch must first grant permission for the cell before the cell can be sent to the switch. After receiving the cell, the switch will route the cell to the final destination.
The buffers are temporary holding areas whose drain rate is normally greater than the fill rate. The cells in these buffers are waiting for a latent period between cell arrival and the chance to deliver the cells to the switch. Thus the number of cells in these buffers is directly proportional to the amount of traffic being sent into the switch.
For certain prior art switches, there are dedicated buffers for each destination accessible via the switch. In a given application specific integrated circuit (ASIC) there can be 15 buffers, each of fixed size, which are contained within the chip. In some of the newer ASIC's there are 122 buffers, each larger than in the previous ASIC because of greater latency times. These 122 buffers no longer fit within the ASIC and are implemented in external RAM at greater expense. The trend is toward more buffers.